Modern processors are increasingly integrating functionality such as graphics, display engines, security engines and others, PCIe™ ports (i.e., ports in accordance with the Peripheral Component Interconnect Express (PCI Express™ (PCIe™)) Specification Base Specification version 2.0 (published Jan. 17, 2007) (hereafter the PCIe™ specification) and other PCI-e™ based peripheral devices.
Processor based products are very complex in design but at the same time have to service a variety of market segments such as server, desktop, mobile, embedded, ultra-mobile and mobile Internet devices. Some markets seek to use single chip system-on-chip (SoC) solutions that combine at least some of processor cores, memory controller hub (MCH), input/output controller (ICH) and other segment specific acceleration elements onto a single chip. However, designs that accumulate these features are slow to emerge due to the difficulty of integrating different intellectual property (IP) blocks on a single die to native internal interconnects.
Some semiconductor integrated circuits (ICs) are implemented in a so-called multi-chip package (MCP) in which two or more die are integrated in a single package. Current techniques involve using a PCIe™ interconnect or other proprietary internal interconnects within the package for die-to-die connectivity. Both of these suffer from drawbacks including power consumption, spacing and routing issues and complexity, and with regard to proprietary designs, a lack of interoperability.